1. Field of the Invention
Generally, the subject matter of the present disclosure relates to microstructure devices, such as integrated circuits, and, more particularly, to metallization layers including highly conductive metals, such as copper, embedded into a dielectric material of reduced permittivity.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
In integrated circuits having minimum dimensions in the sub-micrometer range, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 50 nm and less, thereby continuously enhancing transistor performance, the signal propagation delay is no longer limited by the field effect transistors but is affected, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. The parasitic RC time constants and the capacitive coupling between neighboring metal lines, therefore, require the introduction of a new type of material for forming the metallization layer.
Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by providing a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum suffers from significant electromigration at higher current densities that may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by, for instance, copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a copper-based metallization layer, possibly in combination with a low-k dielectric material, is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Therefore the so-called damascene or inlaid technique is frequently employed in forming metallization layers including copper lines and vias. Typically, in the damascene technique, the dielectric layer is deposited and then patterned for receiving trenches and via openings that are subsequently filled with copper or alloys thereof by plating methods, such as electroplating or electroless plating. Moreover, since copper readily diffuses in a plurality of dielectrics, such as silicon dioxide and in many low-k dielectrics, the formation of a diffusion barrier layer at interfaces with the neighboring dielectric material may be required. Moreover, the diffusion of moisture and oxygen into the copper-based metal has to be suppressed as copper readily reacts to form oxidized portions, thereby possibly deteriorating the characteristics of the copper-based metal line with respect to adhesion, conductivity and the resistance against electromigration.
During the filling in of a conductive material, such as copper, into the trenches and via openings, a significant degree of overfill has to be provided in order to reliably fill the corresponding openings from bottom to top without voids and other deposition-related irregularities. Consequently, after the metal deposition process, excess material may have to be removed and the resulting surface topography planarized, for instance, by using electrochemical etch techniques, chemical mechanical polishing (CMP) and the like. For example, during CMP processes, a significant degree of mechanical stress may be applied to the metallization levels formed so far, which may cause structural damage to a certain degree, in particular when sophisticated dielectric materials of reduced permittivity are used. As previously explained, the capacitive coupling between neighboring metal lines may have a significant influence on the overall performance of the semiconductor device, in particular in metallization levels, which are substantially “capacitance driven,” i.e., in which a plurality of closely spaced metal lines have to be provided in accordance with device requirements, thereby possibly causing signal propagation delay and signal interference between neighboring metal lines. For this reason, so-called low-k dielectric materials or ultra low-k materials may be used, which may provide a dielectric constant of 3.0 and significantly less, in order to enhance the overall electrical performance of the metallization levels. On the other hand, typically, a reduced permittivity of the dielectric material is associated with a reduced mechanical stability, which may require sophisticated patterning regimes so as to not unduly deteriorate reliability of the metallization system.
The continuous reduction of the feature sizes, however, with gate lengths of approximately 40 nm and less, may demand even more reduced dielectric constants of the corresponding dielectric materials, which may increasingly contribute to yield loss due to, for instance, insufficient mechanical stability of respective ultra low-k materials. For this reason, it has been proposed to introduce “air gaps,” at least at critical device areas, since air or similar gases may have a dielectric constant of approximately 1.0, thereby providing a reduced overall permittivity, while nevertheless allowing the usage of less critical dielectric materials. Hence, by introducing appropriately positioned air gaps, the overall permittivity may be reduced while nevertheless the mechanical stability of the dielectric material may be superior compared to conventional ultra low-k dielectrics. For example, it has been proposed to introduce nano holes into appropriate dielectric materials which may be randomly distributed in the dielectric material so as to significantly reduce the density of the dielectric material. However, the creation and distribution of the respective nano holes may require a plurality of sophisticated process steps for creating the holes with a desired density, while at the same time the overall characteristics of the dielectric material may be changed in view of the further processing, for instance with respect to planarizing surface areas, depositing further materials and the like.
In other approaches, advanced lithography processes are additionally introduced to create appropriate etch masks for forming gaps near respective metal lines with a position and size as defined by the lithographically formed etch mask. In this case, however, additional cost-intensive lithography steps may be required, wherein the positioning and the dimensioning of the corresponding air gaps may be restricted by the capabilities of the respective lithography processes. Since, typically, in critical metallization levels, the lateral dimensions of metal lines and the spacing between adjacent metal lines may be defined by critical lithography steps, an appropriate and reliable manufacturing sequence for providing intermediate air gaps may be difficult to be achieved on the basis of the available lithography techniques.
For this reason, in some approaches, self-aligned patterning regimes have been developed in which the dielectric material between closely spaced metal lines may be etched selectively to the material of the metal lines in order to obtain recesses or gaps of a desired depth. Thereafter, an appropriate dielectric material may be deposited such that at least a significant part of the interior volume of the previously formed recesses or gaps may be maintained so that corresponding air gaps are created between two adjacent metal lines. Although this technique may avoid additional lithography steps, the metal lines may be exposed to the reactive etch ambient, thereby contributing to a non-desired erosion of the metal lines. For example, in sophisticated applications, the metal lines including highly conductive metals such as copper and the like may require a reliable cap material that suppresses a diffusion of copper into the surrounding dielectric material and which also suppresses the diffusion of reactive components, such as oxygen, fluorine and the like, to the sensitive copper material. At the same time, a corresponding interface between the cap material and the copper may represent an important factor for determining the overall electrical performance of the metal line in view of its electromigration behavior. Electromigration is a phenomenon in which a significant directed “diffusion” of core atoms may occur in the direction of the electron flow direction upon occurrence of significant current densities in the metal line. In particular, increased diffusion paths may result in a significant material diffusion within the metal line, thereby contributing to a continuous deterioration and finally to a premature failure of the metal line. Consequently, great efforts have been made to provide appropriate cap materials for obtaining a strong interface between the copper and the cap material, which may provide the desired copper confinement and also exhibit superior electromigration behavior. For example, a plurality of conductive cap materials may be used in sophisticated applications which, however, may not exhibit the desired etch resistivity during the above-described self-aligned patterning regime for forming air gaps.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.